FIGS. 13 and 14 show a schematic plan view of a MOSFET and a cross-sectional view along I--I thereof to explain the structure of the MOSFET. In FIG. 13, reference numeral 11 denotes an active area; 12 denotes a gate electrode; 13 denotes a contact portion to a drain electrode in a drain region; and 14 denotes a contact portion to a source electrode in a source region. In the main cross-section (FIG. 14) along I--I that traverses the active region 11 along the gate electrode 12, reference numerals 10, 15, and 16 denote a substrate, a gate oxide film, and field oxide film, respectively.
Normally, the field oxide film 16 is obtained by forming a heat-resistant nitride film, such as, for example, silicon nitride film, on the substrate, and, after the nitride film is patterned by photolithography to a desired geometry, thermally oxidizing the substrate 10 using the remaining nitride film as a mask. During thermal oxidation, a so-called bird's beak is formed in a region extending from the field oxide film 16 to the subsequently formed gate oxide film 15; thus, the effective channel width related to the electrical characteristics of the resulting device, that is, the effective value We of channel width, is smaller than its design value on both sides of the gate oxide film 15 by .DELTA.W1/2, respectively, or by .DELTA.W1 in total.
Typically, the electrical characteristic of the MOSFET is characterized (modeled) in advance, and then MOSFET-based integrated circuitry is designed by using the model. Conventionally, when the electrical characteristic of the MOSFET is modeled, Eq. (1) shown below is applied to the design value W of channel width in consideration of the above-mentioned bird's beak to determine the effective value We of channel width, which is used as a channel width. EQU We=W-(.DELTA.W1/2+.DELTA.W1/2)=W-.DELTA.W1 Eq. (1)
Eq. (1) indicates that the transistor gain of the MOSFET is zero until the design value W of channel width reaches a certain value, that is, .DELTA.W1; thus, it can be said that .DELTA.W1 is an offset value for W. Here, .DELTA.W1 is a fixed value in the MOSFET manufacturing process, and is handled as an independent parameter of the channel width design value W.
However, with the correction of the channel width due to Eq. (1) above, as the channel width becomes more scaled down, the above .DELTA.W1 is not actually fixed, so there is a problem that a difference between the device characteristic predicted and the device characteristic resulting from actual fabrication is considerable.
Thus, for MOSFET modeling for a smaller channel width, a channel width correction equation, as shown in Eq. (2) below, has been proposed considering We varies according to the magnitude of the gate bias (Proc, IEEE Int. Conference on Microelectronic Test Structures, 133-137, Vol. 6, March 1993). Note that Gw (Vgs-Vth) in Eq. (2) represents a term that varies with the gate bias. EQU We=W+.DELTA.W+Gw(Vgs-Vth) Eq. (2)
By considering the dependency of the gate bias as shown in FIG. 2, correction can be made to some degree when the channel width is scaled down; however, there is a problem that modeling is complex and difficult. Additionally, when the channel width is scaled down, the final geometry is physically different than when the channel width is larger; the resulting influence is greater than the gate bias dependency.
It has also been proposed that a so-called Binning method be employed to correct the channel width. The Binning method involves dividing the W/L matrix into multiple areas according to the model fitting accuracy, where W and L are the design values of channel width and channel length, respectively, and performing characterization by use of Eq. (1) for each area, thereby achieving correction in greater detail according to the value of W/L.
With the Binning method, however, there are problems that if the value of W/L is on the boundary of the areas, it is unknown which modeling parameter should better be used, and handling of this case is inconvenient; it is difficult to assure continuity of models between areas; and all of the W/L values cannot be characterized (modeled) accurately. Furthermore, the modeling is complex.
Accordingly, it is an object of the present invention to provide a modeling method of MOSFET that can accurately and simply determine the effective value of channel width based on the design value of channel width when the channel width is scaled down, thereby accurately predicting the electrical characteristic of the MOSFET.